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Espressif Systems /ESP32-P4 /SPI0 /SPI_MEM_USER

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Interpret as SPI_MEM_USER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_MEM_CS_HOLD)SPI_MEM_CS_HOLD 0 (SPI_MEM_CS_SETUP)SPI_MEM_CS_SETUP 0 (SPI_MEM_CK_OUT_EDGE)SPI_MEM_CK_OUT_EDGE 0 (SPI_MEM_USR_DUMMY_IDLE)SPI_MEM_USR_DUMMY_IDLE 0 (SPI_MEM_USR_DUMMY)SPI_MEM_USR_DUMMY

Description

SPI0 user register.

Fields

SPI_MEM_CS_HOLD

spi cs keep low when spi is in done phase. 1: enable 0: disable.
SPI_MEM_CS_SETUP

spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
SPI_MEM_CK_OUT_EDGE

The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.
SPI_MEM_USR_DUMMY_IDLE

spi clock is disable in dummy phase when the bit is enable.
SPI_MEM_USR_DUMMY

This bit enable the dummy phase of an operation.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data